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<p>Structure type to access the Data Watchpoint and Trace Register (DWT).  
</p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d">CTRL</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/W) Control Register.  <a href="#a37964d64a58551b69ce4c8097210d37d"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4">CYCCNT</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) Cycle Count Register.  <a href="#a71680298e85e96e57002f87e7ab78fd4"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc">CPICNT</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) CPI Count Register.  <a href="#a88cca2ab8eb1b5b507817656ceed89fc"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82">EXCCNT</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) Exception Overhead Count Register.  <a href="#ac0801a2328f3431e4706fed91c828f82"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a8afd5a4bf994011748bc012fa442c74d">SLEEPCNT</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) Sleep Count Register.  <a href="#a8afd5a4bf994011748bc012fa442c74d"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#aeba92e6c7fd3de4ba06bfd94f47f5b35">LSUCNT</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/W) LSU Count Register.  <a href="#aeba92e6c7fd3de4ba06bfd94f47f5b35"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab">FOLDCNT</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x018 (R/W) Folded-instruction Count Register.  <a href="#a35f2315f870a574e3e6958face6584ab"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#abc5ae11d98da0ad5531a5e979a3c2ab5">PCSR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x01C (R/ ) Program Counter Sample Register.  <a href="#abc5ae11d98da0ad5531a5e979a3c2ab5"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904">COMP0</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x020 (R/W) Comparator Register 0.  <a href="#a7cf71ff4b30a8362690fddd520763904"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a5bb1c17fc754180cc197b874d3d8673f">MASK0</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x024 (R/W) Mask Register 0.  <a href="#a5bb1c17fc754180cc197b874d3d8673f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729">FUNCTION0</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x028 (R/W) Function Register 0.  <a href="#a5fbd9947d110cc168941f6acadc4a729"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#addd893d655ed90d40705b20170daac59">RESERVED0</a> [1]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#addd893d655ed90d40705b20170daac59"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a4a5bb70a5ce3752bd628d5ce5658cb0c">COMP1</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x030 (R/W) Comparator Register 1.  <a href="#a4a5bb70a5ce3752bd628d5ce5658cb0c"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a0c684438a24f8c927e6e01c0e0a605ef">MASK1</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x034 (R/W) Mask Register 1.  <a href="#a0c684438a24f8c927e6e01c0e0a605ef"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747">FUNCTION1</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x038 (R/W) Function Register 1.  <a href="#a3345a33476ee58e165447a3212e6d747"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a069871233a8c1df03521e6d7094f1de4">RESERVED1</a> [1]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a069871233a8c1df03521e6d7094f1de4"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a8927aedbe9fd6bdae8983088efc83332">COMP2</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x040 (R/W) Comparator Register 2.  <a href="#a8927aedbe9fd6bdae8983088efc83332"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a8ecdc8f0d917dac86b0373532a1c0e2e">MASK2</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x044 (R/W) Mask Register 2.  <a href="#a8ecdc8f0d917dac86b0373532a1c0e2e"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b">FUNCTION2</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x048 (R/W) Function Register 2.  <a href="#acba1654190641a3617fcc558b5e3f87b"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a8556ca1c32590517602d92fe0cd55738">RESERVED2</a> [1]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#a8556ca1c32590517602d92fe0cd55738"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a3df15697eec279dbbb4b4e9d9ae8b62f">COMP3</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x050 (R/W) Comparator Register 3.  <a href="#a3df15697eec279dbbb4b4e9d9ae8b62f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#ae3f01137a8d28c905ddefe7333547fba">MASK3</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x054 (R/W) Mask Register 3.  <a href="#ae3f01137a8d28c905ddefe7333547fba"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890">FUNCTION3</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x058 (R/W) Function Register 3.  <a href="#a80bd242fc05ca80f9db681ce4d82e890"></a><br/></td></tr>
</table>
<hr/><h2>Field Documentation</h2>
<a class="anchor" id="a7cf71ff4b30a8362690fddd520763904"></a><!-- doxytag: member="DWT_Type::COMP0" ref="a7cf71ff4b30a8362690fddd520763904" args="" -->
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